1. Field of the Invention
The subject invention relates generally to processing systems for semiconductor technology and, more specifically, to a semiconductor wafer processing chuck for semiconductor wafer processing tools.
2. Background Information
Semiconductor devices such as integrated circuits (ICs) form at least part of almost every electronic product. As semiconductor technology advances, the complexity of integrated circuits increases. This increased complexity typically results in smaller integrated circuit elements and/or components. Because of the decrease in size of the circuit elements, the techniques for producing the circuit elements, and thus the integrated circuit itself, need to be quite precise. Problems in wafer processing or defects introduced during such wafer processing can result in bad or defective integrated circuits.
The many semiconductor processing steps utilize various semiconductor processing tools. Such processing tools include deposition devices of many types, photolithography devices, polishing devices and/or the like. Most, if not all, of these devices utilize what is known as a wafer chuck mechanism to hold the semiconductor wafer for processing. In FIG. 1, a typical (prior art) wafer chuck mechanism 10 is shown. The wafer chuck mechanism 10 of FIG. 1 is depicted in cross-section for clarity.
The wafer chuck mechanism 10 includes a wafer chuck 12. The wafer chuck 12 is typically annular in shape to conform to the generally annular shape of semiconductor wafers. The wafer chuck 10 has a shield ring 14 that is disposed on an outer annular periphery of the upper surface thereof. A plurality of wafer pins 16 fixedly extend axially upward from an upper surface of the wafer chuck 12. The wafer pins 16 are adapted to support a semiconductor wafer 20 above the surface of the wafer chuck. Particularly, the top of the wafer pins 16 contact a lower or bottom surface (backside) 24 of the semiconductor wafer 20 to hold the semiconductor wafer 20 flat. Processing is performed on the top or upper surface 22 of the semiconductor wafer 20.
It should be appreciated that the wafer pins 16 are enlarged for clarity. Typically, wafer pins have a dimension on the order of 0.07065 mm2. A typical wafer chuck has approximately 5827 pins. Additionally, the wafer chuck has other parts that can contact the backside of the semiconductor wafer. These other parts have an approximate area of 583.54 mm2. Thus, approximately 5.4% of the backside area of the semiconductor wafer is in contact with components of the wafer chuck.
The wafer chuck mechanism 10 utilizes suction (i.e. a vacuum or exhaustion of air) in order to retain the semiconductor wafer 20 onto the wafer pins 16 of the wafer chuck 12 for processing. As shown in FIG. 1, the wafer chuck 12 includes a plurality of suction or air exhaustion ports or bores 18. A suction, vacuum or air exhaustion device (not shown) is in communication with the ports 18. The air suction (represented by the arrows emanating from the bores 18) pulls the semiconductor wafer 20 onto the wafer pins 16. The vacuum or suction force is maintained during wafer processing. This aids in securely retaining the semiconductor wafer 20 onto the wafer chuck mechanism 10.
For various reasons, certain areas of the backside of the semiconductor wafer may become contaminated during one or more of the various processing steps (not including solvent and scrubber cleaning steps). Particularly, various areas of the backside of the semiconductor wafer may have particle contamination after one or more wafer processing steps. For example, after chemical vapor deposition (CVD) the backside of the semiconductor wafer may have as many as 5000 particles of contamination scattered thereabout ranging in size from about 2.9 xcexcm and smaller. Likewise, after sputtering, the backside of the semiconductor wafer may have as many as 1100 particles of contamination scattered thereabout ranging in size from about 2.9 xcexcm and smaller. Additionally, after resist coating, the backside of the semiconductor wafer may have as many as 1400 particles of contamination scattered thereabout ranging in size from about 2.9 xcexcm and smaller.
Such contamination may lead to or cause defects in wafer processing. One such defect that can occur during photolithography processing of the semiconductor wafer is known as xe2x80x9chot spot.xe2x80x9d Hot spot is induced by wafer backside contamination resulting from previous wafer processing. If the contamination on the wafer backside happens to register with one of the pins 18 of the wafer chuck 12, defocusing during the photolithography process may occur around a small region of the wafer surface opposite the contamination.
Referring to FIG. 2, the problem of hot spot is graphically illustrated. In FIG. 2, a particle of contamination 26 on the backside 24 of the semiconductor wafer 20 is shown registered with (on top of) wafer pin 16a. The suction pulling down on the backside 24 of the wafer 20 causes a deformity 30 to occur in the wafer 20. The deformity 30 creates a bump, bulge or the like on or to the upper or topside surface 22 of the semiconductor wafer 20. Thus, rather than the upper surface 22 being generally planar, the upper surface 22 now has a topology. It should be appreciated that FIG. 2 shows only one hot spot, but there may be many more on the wafer.
FIG. 3 is a graph 34 illustrating how backside contamination can affect photolithography processing of the semiconductor wafer. Particularly, the graph 34 of FIG. 3 correlates the height of backside contamination (in xcexcm) along the x-axis to the defocus on the wafer surface (in xcexcm) along the y-axis caused by the contamination. As can be seen from the five plotted points, the greater the height of the backside contamination, the greater the defocus. Such correlation, however, is not linear.
Such defocusing due to hot spot can induce incomplete patterns for the formation of integrated circuit components, like short metal lines, broken metal lines, unlanded vias, and unlanded contact holes. Periodic visual inspection for production wafers has heretofore been done utilizing an ultraviolet light visual inspection tool. The affected wafer will exhibit refraction and diffraction anomalies at the hot spot region. Visual inspection for hot spot may also be accomplished on every production wafer after the mask process. Because, production wafers typically have several previously printed mask patterns, it is difficult to visually detect hot spot.
In view of the above it should be appreciated that it is thus very difficult to visually and/or periodically detect hot spot in all cases. Moreover, it is difficult to reduce or eliminate backside contamination during the various processing steps.
What is therefore needed in view of the above, is a system, method and/or apparatus for alleviating semiconductor wafer production problems associated with hot spot.
The above needs are addressed by a system, apparatus and/or method that compensates for semiconductor backside contamination during processing of the semiconductor wafer. Particularly, the subject invention is a wafer chuck assembly that compensates for backside contamination on a semiconductor wafer during photolithography processing of the semiconductor wafer.
In one form, the subject invention provides a method of retaining a semiconductor wafer for processing. The method includes the steps of: (a) placing a semiconductor wafer onto a wafer chuck having height adjustable wafer support pins and a shield ring; (b) applying a biasing force to each wafer support pin; and (c) applying suction to a backside of the semiconductor wafer.
In another form, the subject invention is a wafer chuck assembly. The wafer chuck assembly includes a wafer chuck, a suction bore in the wafer chuck and adapted to be connected to an air suction device, a plurality of pin bores in the wafer chuck, and a support pin axially movably disposed in each one of the plurality of pin bores.
In yet another form, the subject invention is a wafer chuck assembly for a semiconductor wafer processing device. The wafer chuck assembly includes a wafer chuck body having an upper surface and a lower surface, a shield ring disposed on the upper surface of the wafer chuck body, means for providing suction to the upper surface of the wafer chuck body, and support means disposed in the upper surface of the wafer chuck body for receiving a backside contaminated semiconductor wafer for processing and providing a relatively planar processing surface for the backside contaminated semiconductor wafer.
The subject invention provides the ability to compensate for semiconductor wafer backside contamination, particularly areas of which register with wafer support pins, that aids in alleviating hot spot during wafer processing. This provides a relatively planar upper or processing surface for processing.